When does the ARM7 processor increase its PC register?
I've been thinking about this question for a while: when an ARM7 processor (with 3 pipelines) increases its PC register.
I originally thought that after the instruction was executed, the first check of the processor is there any exception in the last execution, and then increasing on the PC by 2 or 4 depending on the current state. If an exception is thrown, ARM7 will change its operating mode, save the PC in the LR of the current mode, and begin to handle the current exception without changing the PC register.
But that doesn't make sense when parsing the returning instructions. I cannot figure out why the PC would be assigned LR when returning from an undefined -instruction exception, while LR-4 from a prefetch-abort exception, did not both of these exceptions occur in the decode state? Moreover, according to my tutorial, the PC will always be assigned LR-4 when returning from a prefetch-abort exception, no matter what state the processor has (ARM or Thumb) before the exception. However, I think the PC should be assigned LR-2 if the initial state is Thumb, since the Thumb instruction is 2 bytes instead of the 4 bytes that the ARM instruction has and we just want to rollback the command in its current state. whether there are flaws in my reasoning or something wrong with the tutorial.
Seems like a long question. I really hope someone can help me get the correct answer.
Thanks in advance.
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You fall back to LR from an undefined statement because it points to the statement after the one that caused the hook; you don't want to go back to the same undefined statement again, it will only fall into the same trap.
You fall back to LR-4 from prefetch-abort if you want to execute the same statement again; presumably because you mapped some memory for it to make it work now.
At what point in the pipeline ARM7 actually enlarges its PC, it doesn't matter, since the PC's runtime value and therefore the LR value in interrupt handlers is something spelled out as part of the ARM architecture standard based largely on the ancient ARM2 made with my PC.
However, I think PC should be assigned LR-2 if the initial state is Thumb
It makes sense, but then the exception handler needs to know if the source code that caused it to run was ARM or Thumb code. This may have affected compatibility, as there were many non-Thumb exception handling code around. So instead of Thumb Fudged LR architecture when entering exception handlers so that the handler can always use the same statement to return, the one they used to use for non-Thumb code.
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