L1 / 2 cache problem
It is possible that main memory is stored in the cache more than once. Obviously this is true and is common on multiprocessor machines. But even on uniprocessor machines, this can happen.
Consider a Pentium processor with a shared L1 instruction / data cache. The instructions only go to the I-cache, the data is specific to the D-cache. Now, if the OS allows self-modifying code, the same memory can be loaded into both I- and D-caches, once as data, once as instructions. Now you have this data twice in the L1 cache. Therefore, for a CPU with such a split cache architecture, the cache consistency protocol must be used to avoid race conditions / corruption.
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Each cache stores some small subset of all memory. When the CPU needs a word from memory, it first goes to L1, then L2 cache, and so on, before the main memory is checked . Thus, a certain memory word can be in L2 and L1 at the same time, but it cannot be stored twice in L1 because it is not necessary.
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Yes maybe. The copy of L1 is being updated, but has not been flushed to L2. This only happens if L1 and L2 are non-exclusive caches. This is obvious for uni-processors, but even more so for multiprocessors, which usually have their own L1 caches for each core.
It all depends on the cache architecture - whether or not it guarantees anything.
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