How to determine the clock input in Xilinx
Hey, I have almost no experience with Xilinx. I have a group project for a Digital Logic course due to take place soon when my partner who was supposed to take care of the Xilinx simulations decided to vouch for me. So I'm trying to figure it out at the last minute.
I have developed a synchronous counter using multiple JK flip flops and I need to define the CLK input for FJKC.
I have worked out the correct circuit, but I cannot figure out how to determine the clock input.
Any help is appreciated and yes this is homework. I just can't find any basic xilinx documentation / tutorials on the internet, and I honestly don't have time to learn the whole IDE.
I am using VHDL
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Check out this example.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all; -- for the unsigned type
entity counter_example is
generic ( WIDTH : integer := 32);
port (
CLK, RESET, LOAD : in std_logic;
DATA : in unsigned(WIDTH-1 downto 0);
Q : out unsigned(WIDTH-1 downto 0));
end entity counter_example;
architecture counter_example_a of counter_example is
signal cnt : unsigned(WIDTH-1 downto 0);
begin
process(RESET, CLK) is
begin
if RESET = '1' then
cnt <= (others => '0');
elsif rising_edge(CLK) then
if LOAD = '1' then
cnt <= DATA;
else
cnt <= cnt + 1;
end if;
end if;
end process;
Q <= cnt;
end architecture counter_example_a;
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Imagine you have an example device like this:
ENTITY SampleDevice IS
PORT
(
CLK : IN std_logic
);
END SampleDevice;
To connect CLK signal to real clock input in FPGA, you have to set it as Top Module and create UCF file with entry:
NET "CLK" LOC = "P38";
The P38 is the clock input to the Xilinx Spartan 3 XC3S200.
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