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Optimal memory layout for read-only memory segments

Suppose I have two memory segments (equal size of each, approximately 1kb), one is read-only (after initialization) and the other is read / write.

What is the best in-memory layout for such segments in terms of memory performance? one distribution, contiguous segments, or two distributions (in general, not contiguous). my main architecture is Linux 64-bit.

I feel the same (more cache friendly) case better. Are there circumstances where the second layout is preferred?

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I would put 2KB of data in the middle of the 4KB page to avoid read / write interference close to the page border. Likewise, keeping separate recording data is also a good idea for the same reason.

Having contiguous read / write blocks can be less efficient than splitting them up. For example, a cache that stores data for code that is only interested in a read-only part may become invalid as a result of a write from another processor. The cache line will be invalidated and updated even if the code does not read the data being written. By keeping the blocks separate, you avoid this case and write to the writeable block of data only for invalid cache lines for the writeable block, and do not interfere with the cache lines for the read-only block.



Note that this is only a problem at the block boundary between read and write blocks. If your block sizes were much larger than the cache line size, that would be a peripheral issue, but since your blocks are small, requiring only a few cache lines, the problem with invalid lines can be significant.

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With this little data, it really doesn't matter much. Both of these arrays will fit into any level cache.



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It will depend on what you are doing with the memory. I'm pretty sure contiguous (and aligned pages!) Will never be slower than two randomly spaced segments, but it won't necessarily be faster.

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Considering this is an Intel processor, you probably only need to make sure the addresses are not multiples of 64k apart. If present, loads from any section that are mapped to the same address modulo 64k will collide at L1 and cause L1 gaps. There's also a 4MB alias issue, but I would be surprised if you run into this.

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